Testing a semiconductor device generally includes performing a quiescent current (IDDQ) test. IDDQ testing of some semiconductor devices, however, may yield unstable and unreliable results. For example, a system-on-chip (SOC) device may comprise a large amount of integrated cores and transistors that may yield a significant leakage current during IDDQ testing. Ignoring the leakage current may yield inaccurate performance predictions of the SOC device. The leakage current may be reduced or eliminated by powering down the logic blocks of the semiconductor device.
A known technique for performing IDDQ testing involves designing the SOC device with separate power supplies for each logic block of the semiconductor device so that each logic block may be powered down. This known technique, however, requires that the device have multiple dedicated power supplies, which may result in increased size of the package, increased number of pins, extended design cycle, and delayed ramp-to-production (RTP) time. Moreover, semiconductor devices with an insufficient number of dedicated power supplies may require alteration. Consequently, known techniques for IDDQ testing of a semiconductor device are unsatisfactory in certain situations.